Heterogeneity in parallel and distributed computing

Heterogeneity is one of the most profound and challenging features of today’s parallel and distributed computing systems. From the macro level, where networks of distributed computers, composed by diverse node architectures, are interconnected with potentially heterogeneous networks, to themicro level,where deeper memory hierarchies, heterogeneousmulticores, and various accelerator architectures are increasingly common, the impact of heterogeneity on all computing tasks is increasing rapidly. This special issue on heterogeneity in parallel and distributed computing is inspired by the great success of the 21st International Heterogeneity in Computing Workshop (HCW 2012, held in Shanghai, China, in May 2012, in conjunction with IPDPS), which attracted 41 high-quality submissions, 17 of which were accepted for presentation and publication in the workshop proceedings. All submissions to this special issue, both extended versions of some HCW 2012 papers and many external original manuscripts, were rigorously reviewed by top-quality experts in the field. The result of the collective efforts of the reviewers and all the authors that submitted their work is this issue, featuring 15 accepted papers. They cover a wide range of topics from multicore processor architecture to scheduling algorithms. A brief outline of the contents of each paper is given in the following paragraphs. The first two papers evaluate two recent on-chip multiprocessor architectures. In the paper ‘‘Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture’’, Jaekyu Lee et al. study a perspective heterogeneous chip multiprocessor architecture integrating on the same chip both CPU andGPU cores. In this architecture, the on-chip interconnection network is used to control the access to the resources shared by the CPU and GPU cores. The study focuses on the impact of this interconnection network on the overall performance of the architecture when CPU and GPGPU applications run simultaneously, and suggests an optimal ring interconnection network. In the paper ‘‘Sparsematrix–vectormultiplication on the singlechip Cloud computer many-core processor’’, Juan C. Pichel and Francisco F. Rivera study the performance potential and power efficiency of an experimental 48-core Intel processor, Single-Chip Cloud Computer (SCC), for execution of such an irregular application as sparse matrix–vector multiplication. The next paper, ‘‘Energy-efficientmultithreading for a hierarchical heterogeneous multicore through locality–cognizant thread’’, by Patrick Anthony La Fratta and Peter M Kogge, deals with a novel heterogeneous multicore processor architecture, passive/ active multicore, proposed by the authors in their previous publications. In this paper, the authors present energy-efficient multithreading techniques for this architecture. A compute node consisting of a multicore CPU and a GPU accelerator as well as HPC systems built from such compute nodes are getting more and more common. The next three papers study